12231 The Translation Table Entry
Each entry of the TLB consists of a Translation Table Entry (TTE), which describes the mapping and provides details of its associated properties. The TTE may be thought of as corresponding to a page table entry, or PTE, in the sun4m architecture. A TTE is made up of two components, the tag and the translation data, each of length 64 bits. The TTE tag contains the encoded virtual address and context ID (Figure 12.7), and the TTE data contains the corresponding physical address together with various properties associated with the translation (Figure 12.6). The context ID is a 13-bit quantity which is used to distinguish between different address spaces, so that the same virtual addresses in different address spaces can coexist in the TLB. One of the most significant properties of the mapping is its size. Each TTE maps a contiguous area of memory, which can be 8 Kbytes, 64 Kbytes, 512 Kbytes or 4 Mbytes in size (and additionally 32 Mbytes and 256 Mbytes on UltraSPARC V+). Note that this mapping size is not directly related to the underlying virtual page size, which
remains at 8 Kbytes (see Section 9.10.1). Other properties of the mapping include the write and execute permissions and cacheability in the physically-indexed and virtually-indexed caches.
Figure 12.6. TTE Data Fields
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TTE Data:
CP: Cache in physically indexed cache CV: Cache in virtually indexed cache E: Side effect
EX: Execute permission bit G: Global bit
HNUM; Number of sf hrnents in hme blk
IE;: Invert endianness bit
IMV: TSB entry invalid bit
L: Lock in TLB
LCK: TSB entry locked bit
LCKCNT: TTE lock reference count
MFO: No-fault access only
NQS: No sync bit
P: Privileged bit
Ref: Reference bil
Size; Page size
Soft: Software defined fields
V: Valid bit
W;; Writeable bit
WR: Write permission bit
Note: On UitraSPARCi/ti TTE Data bits <49:41> am userf tor diagnostic access.
Figure 12.7. Hardware and Software Representations of the TTE Tag
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